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Latch-Up Problem in CMOS – VLSI Design – Buzztech
LogicBlocks Experiment Guide - SparkFun Learn
EEVblog #16 - CMOS SCR Latchup Tutorial - YouTube
Analog IC co-design for latch-up compliance - EDN Asia
Analog IC co-design for latch-up compliance - EDN Asia
[SOLVED] - How to use SCR as a Latch? | Forum for Electronics
Latch-up issue in CMOS Logic | Latch-up effect in VLSI - Team VLSI
Latchup and its prevention in CMOS devices